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59. A. Goundan and J. P. Hayes, Identification of equivalent faults in logic networks, IEEE Trans.

Rudell, Dynamic variable ordering for ordered binary decision diagrams, Proc. IEEE Int. Conf. -Aided Des. (ICCAD ’93), 1993. 12. K. S. Brace, R. L. Rudell, and R. E. Bryant, Efficient implementation of a bdd package, Proc. 27th ACM/IEEE Des. Autom. , 1990, pp. 40–45. 13. J. C. Madre and J. P. Billon, Proving circuit correctness using formal comparison between expected and extracted behavior, Proc. 25th ACM/IEEE Des. Autom. , 1988, pp. 205–210. 14. D. Brand, Verification of large synthesized designs, Proc.

37. M. Abramovici and M. A. Breuer, Fault diagnosis based on effectcause analysis, Proc. 24th ACM/IEEE Des. Autom. , 1987, pp. 69–76. DESIGN VERIFICATION AND FAULT DIAGNOSIS IN MANUFACTURING 38. E. M. Rudnick, W. K. Fuchs, and J. H. Patel, Diagnostic fault simulation of sequential circuits, Proc. Int. , 1992, pp. 178–186. 39. S. , Rapid diagnostic fault simulation at stuck-at faults in sequential circuits using compact lists, Proc. 32nd ACM/IEEE Des. Autom. , 1995, pp. 133–138. 40. S. Venkataraman, I.

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